IPC J-STD-012

This informative document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include design considerations, assembly processes, technology choices, application and reliability data. Chip packaging variations include flip chip, HDI, micro BGA, micro SMT and SLICC. Also provides general information on implementing flip chip and chip scale technologies for creating multichip modules, I/C cards, memory cards and very dense surface mount assemblies. Co- developed by IPC, EIA, MCNC and Sematech.



Product Code(s): J-012(D)1

This product is related to: IPC J-STD-013 - Implementation of Ball Grid Array and Other High Density Technology
IPC J-STD-026 - Semiconductor Design Standard for Flip Chip Applications
IPC J-STD-028 - Performance Standard fo Construction of Flip Chip and Chip Scale Bumps
IPC M-103 - Standards for Surface Mount Assemblies Manual
IPC SM-784 - Guidelines for Chip-on-Board Technology Implementation
IEC/PAS 62084 Ed. 1.0 en:1998 - Implementation of flip chip and chip scale technology
IPC J-STD-013 - Implementation of Flip Chip and Chip Scale Technology
IPC J-STD-026 - Implementation of Flip Chip and Chip Scale Technology
IPC J-STD-028 - Implementation of Flip Chip and Chip Scale Technology
IPC M-103 - Implementation of Flip Chip and Chip Scale Technology
IPC SM-784 - Implementation of Flip Chip and Chip Scale Technology