IPC J-STD-028

This new standard establishes construction detail requirements for bumps and other terminal structures used for Flip Chip and Chip Scale carriers. The specific standards for different terminations are appropriately matched to a particular interconnection process and include such diverse terminations as solder bumps, columns, non-melting stand-offs and conductive polymer deposits. The document articulates a set of designations and expectations for product performance for the manufacture and the user of flip chip or chip scale devices. Recommendations are provided for options and flexibility to implement best commercial practices and evolving process improvements.



Product Code(s): J-028(D)1

This product is related to: IPC J-STD-012 - Implementation of Flip Chip and Chip Scale Technology
IPC J-STD-026 - Semiconductor Design Standard for Flip Chip Applications
IPC SM-784 - Guidelines for Chip-on-Board Technology Implementation
IPC J-STD-012 - Performance Standard fo Construction of Flip Chip and Chip Scale Bumps
IPC J-STD-013 - Performance Standard fo Construction of Flip Chip and Chip Scale Bumps
IPC J-STD-026 - Performance Standard fo Construction of Flip Chip and Chip Scale Bumps
IPC SM-784 - Performance Standard fo Construction of Flip Chip and Chip Scale Bumps