Full Description

Scope

This standard defines the e functional verification language. This standard aims to serve as an authoritative source for the definition of (a) syntax and semantics of e language constructs, (b) the e language interaction with standard simulation languages, and (c) e language libraries.

Purpose

This standard serves the community involved with functional verification of electronic designs using the e language. It provides an implementation independent definition of the e language and facilitates the development of e language based design automation tools.

Abstract

Revision Standard - Inactive - Superseded.The e functional verification language is an application-specific programming language, aimed at automating the task of verifying a hardware or software design with respect to its specification. Verification environments written in e provide a model of the environment in which the design is expected to function, including the kinds of erroneous conditions the design needs to withstand. A typical verification environment is capable of generating user-controlled test inputs with statistically interesting characteristics. Such an environment can check the validity of the design responses. Functional coverage metrics are used to control the verification effort and gauge the quality of the design. e verification environments can be used throughout the design cycle, from a high-level architectural model to a fully realized system. A definition of the e language syntax and semantics and how tool developers and verification engineers should use them are contained in this standard.

Product Details

Published: 08/26/2011 ISBN(s): 9780738180199, 9780738180205, 9780738166872 Number of Pages: 495File Size: 1 file , 2.4 MBRedline File Size:3files, 9.6 MB Product Code(s): STDRL97128, STDSU97128, STDPDRL97128